Extending NVLink to chip-level integration.
NVIDIA® NVLink®-C2C extends the industry-leading NVLink technology to a chip-to-chip interconnect. This enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon.
The design and layout of a chip-to-chip interconnect is vital to proper function, performance, power efficiency, reliability, and fabrication yield. NVIDIA NVLink-C2C is built on top of the world-class SerDes and Link design technology. With advanced packaging, NVLink-C2C interconnect delivers up to 25X more energy efficiency and 90X more area-efficiency than a PCIe Gen 5 PHY on NVIDIA chips. NVLink-C2C is extensible from PCB-level integration, multi-chip modules (MCM), and silicon interposer or wafer-level connections, enabling the industry’s highest bandwidth, while optimizing for both energy and area efficiency. The NVLink-C2C technology will be available for customers and partners who want to create semi-custom system designs.
The NVIDIA GB200 combines two Blackwell GPUs and an NVIDIA Grace™ CPU connected over NVLink-C2C for a fully coherent CPU+GPU that defines the next era of generative AI.
The NVIDIA Grace Hopper™ Superchip combines the Grace and Hopper architectures using NVIDIA NVLink-C2C to deliver a CPU+GPU coherent memory model for accelerated AI and high-performance computing (HPC) applications.
NVIDIA Grace CPU Superchip uses the NVLink-C2C technology to deliver 144 cores and 1 TB/s of memory bandwidth for cloud, enterprise, and high-performance computing.
Supports high-bandwidth coherent data transfers between processors and accelerators.
Supports atomics between processors and accelerators to perform fast synchronization and high-frequency updates to shared data.
Uses advanced packaging to deliver 25X more energy efficiency and 90X more area-efficiency than PCIe Gen 5 PHY on NVIDIA chips.
Supports Arm’s AMBA CHI (Coherent Hub Interface) or Compute Express Link (CXL) industry standard protocols for interoperability between devices.
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